supertex inc. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com HV5623 block diagram 32-channel serial to parallel converter with open drain outputs general description the HV5623 is a low-voltage serial to high-voltage parallel converter with open drain outputs. this device has been designed for use as a driver for ac-electroluminescent displays. it can also be used in any application requiring multiple output high voltage current sinking capabilities, such as driving inkjet and electrostatic print heads, plasma panels, and vacuum luorescent or large matrix lcd displays. this device consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity selection and blanking of the outputs. data are shifted through the shift register on the high to low transition of the clock. the HV5623 shifts in a clockwise direction when viewed from the top of the package. a data output buffer is provided for cascading devices. this output relects the current status of the last bit of the shift register. operation of the shift register is not affected by the le (latch enable), bl (blanking), or pol (polarity) inputs. transfer of data from the shift register to the latch occurs when the le (latch enable) input is high. the data in the latch is stored when le is low. pol blle data input clk data output hv out 1 (outputs 3 to 30 not shown) latch latch hv out 2 hv out 31 hv out 32 latchlatch 32-bit shift register features ? processed with hvcmos ? technology ? sink current minimum 100ma ? shift register speed 16mhz ? polarity and blanking inputs ? cmos compatible inputs applications ? inkjet and electrostatic print heads ? ac-electroluminescent displays ? mems applications downloaded from: http:///
2 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com HV5623 ordering information device high voltage output hv out (max v) 44-lead qfn 7.00x7.00mm body, 0.80mm height (max), 0.50mm pitch HV5623 220 HV5623k7-g -g indicates package is rohs compliant (green)absolute maximum ratings parameter value supply voltage, v dd 1 -0.5v to +7.0v output voltage, hv out 1 -0.5v to +230v logic input levels 1 -0.5v to v dd +0.5v ground current 2 1.5a continuous total power dissipation 3 3.4w operating temperature range -40c to +85c storage temperature range -65c to +150c maximum junction temperature +125c thermal resistance ( ja ) 3 29 o c/w notes: 1. voltages are referenced to v ss . 2. duty cycle is limited by the total power dissipated in the package.3. 1.0oz 4-layer 3x4 pcb. pin coniguration operating supply voltages and conditions sym parameter min typ max units conditions v dd logic supply voltage 4.5 - 5.5 v --- hv out high voltage output -0.3 - +220 v --- v ih high-level input voltage 0.8v dd - v dd v --- v il low-level input voltage 0 - 0.2v dd v --- f clk clock frequency - - 16 mhz --- t a operating free-air temperature -40 - +85 c --- notes: power-up sequence should be the following: 1. connect ground. 2. apply v dd . 3. set all inputs to a known state. power-down sequence should be the reverse of the above. product marking 44-lead qfn (k7) 1 44 l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = green packagin g HV5623k7 lllllllll yyww aaa ccc 44-lead qfn (k7) (top view) package may or may not include the following marks: si or downloaded from: http:///
3 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com HV5623 dc electrical characteristics (over operating supply voltages and temperature, unless otherwise noted) sym parameter min typ max units conditions i dd v dd supply current - - 25 ma f clk = 16mhz, f data = 8.0mhz i ddq quiescent v dd supply current - - 100 a d in = 0v, all input logic pins = 0v, all outputs off i o(off) off state output current - - 10 a all outputs high, all switches parallel i ih high-level logic input current - - 1.0 a v ih = v dd i il low-level logic input current - - -1.0 a v il = 0v v oh high level output v dd -1.0v - - v id out = -10ma v ol low level output hv out - - 15 v ihv out = +100ma data out - - 1.0 v id out = +10ma v oc hv out clamp voltage - - -1.5 v i ol = -100ma ac electrical characteristics (v dd = 5.0v, t j = 25 o c) sym parameter min typ max units conditions f clk clock frequency - - 16 mhz --- t w clock high / low pulse width 31 - - ns --- t su data setup time before clock falls 25 - - ns --- t h data hold time after clock falls 10 - - ns --- t on turn on time, hv out from enable - - 400 ns r l = 2.0k? to v pp max t dhl delay time clock to data high to low - - 35 ns c l = 15pf t dlh delay time clock to data low to high - - 35 ns c l = 15pf t dle delay time clock to le low to high 20 - - ns --- t wle width of le pulse 20 - - ns --- t sle le set-up time before clock falls 20 - - ns --- c in digital logic input capacitance - - 15 pf --- input and output equivalent circuits vdd data input hv out logic inputs dataoutput logic data output high voltage outputs vdd vss vss vss downloaded from: http:///
4 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com HV5623 switching waveforms le hv ou t w/ s/r high data vali d 50% data inpu t clk data output t su t h t wh t wl 50% t dlh t dhl 50% t wle t dle t sle 50% 50% 10% t on v ih v il v ih v il v oh v ol v oh v ol v ih v il v oh v ol 50% 50% 50% 50% 50% function table function inputs outputs data clk le bl pol shift reg 1 2...32 hv outputs 1 2...32 data out * all on x x x l l * * ... * on on...on * all off x x x l h * * ... * off off...off * invert mode x x l h l * * ... * * * ... * * load s/r h or l l h h h or l * ... * * * ... * * load latches x h or l h h * * ... * * * ... * * x h or l h l * * ... * * * ... * * transparent latch mode l h h h l * ... * off * ... * * h h h h h * ... * on * ... * * notes: h = high level, l = low level, x = irrelevant, = high-to-low transition, = low-to-high transitio n * = dependent on previous stages state before the last clk or last le high. downloaded from: http:///
5 supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: 408-222-8888 www.supertex.com HV5623 pin # function description 1 hv out 22 high voltage outputs. 2 hv out 21 3 hv out 20 4 hv out 19 5 hv out 18 6 hv out 17 7 hv out 16 8 hv out 15 9 hv out 14 10 hv out 13 11 hv out 12 12 hv out 11 13 hv out 10 14 hv out 9 15 hv out 8 16 hv out 7 17 hv out 6 18 hv out 5 19 hv out 4 20 hv out 3 21 hv out 2 22 hv out 1 23 data out data output pin. 24 n/c no internal connection. 25 n/c 26 n/c 27 pol inverts the polarity of the hv out pins 28 clk clock pin, shift registers shifts data on falling edge of input clock. 29 vss reference voltage, usually ground. 30 vdd logic supply voltage. 31 le latch enable pin, data is shifted from shift register to latches on logic input high. 32 data in data input pin. 33 bl blanking pin sets all hv out pins on or off depending upon state of polarity. see function table. 34 n/c no internal connection. 35 hv out 32 high voltage outputs. 36 hv out 31 37 hv out 30 38 hv out 29 39 hv out 28 40 hv out 27 41 hv out 26 42 hv out 25 43 hv out 24 44 hv out 23 center tab connect to vss pin description downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. supertex inc . does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2011 supertex inc. a ll rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com 6 HV5623 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-HV5623 a062111 44-lead qfn package outline (k7) 7.00x7.00mm body, 0.80mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.70 0.00 0.20 ref 0.18 6.85* 5.00 ? 6.85* 5.00 ? 0.50 bsc 0.45 ? 0.00 0 o nom 0.75 0.02 0.25 7.00 5.15 ? 7.00 5.15 ? 0.55 ? - - max 0.80 0.05 0.30 7.15* 5.25 ? 7.15* 5.25 ? 0.65 ? 0.15 14 o jedec registration mo-220, variation wkkd-3, issue k, june 2006 * this dimension is not speciied in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-44qfnk77x7p050, version a122309. notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. seating plane top vi ew side view bottom view a a1 d e a3 l l1 note 3 note 2 note 1 (index area d/2 x e/2) 1 44 1 44 view b note 1 (index area d/2 x e/2) b e e2 d2 x4 vi ew b downloaded from: http:///
|
